View STK15C88-NF45_8360895.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

stk15c88 256-kbit (32 k 8) powerstore nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50593 rev. *e revised march 13, 2014 256-kbit (32 k 8) powerstore nvsram features 25 ns and 45 ns access times pin compatible with industry standard srams automatic nonvolatile store on power loss nonvolatile store under software control automatic recall to sram on power up unlimited read/write endurance unlimited recall cycles 1,000,000 store cycles 100 year data retention single 5 v + 10% power supply commercial and industrial temperatures 28-pin (300 mil and 330 mil) soic packages rohs compliance functional description the cypress stk15c88 is a 256kb fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap? technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. powerstore nvsram products depend on the intrinsic system capacitance to maintain system power long enough for an automatic store on power loss. if the power ramp from 5 volts to 3.6 volts is faster than 10 ms, consider our 14c88 or 16c88 for more reliable operation. logic block diagram not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 2 of 18 contents pin configurations ........................................................... 3 device operation .............................................................. 4 sram read ....................................................................... 4 sram write ....................................................................... 4 autostore operation ........................................................ 4 hardware recall (power up) ........................................ 4 software store ............................................................... 4 software recall ............................................................. 4 hardware protect .............................................................. 5 noise considerations ....................................................... 5 low average active power .............................................. 5 best practices ................................................................... 5 maximum ratings ............................................................. 7 dc electrical characteristics .......................................... 7 data retention and endurance ....................................... 8 capacitance ...................................................................... 8 thermal resistance .......................................................... 8 ac test conditions .......................................................... 8 ac switching characteristics ......................................... 9 sram read cycle ............................................................. 9 switching waveforms ...................................................... 9 sram write cycle .......................................................... 10 switching waveforms .................................................... 10 autostore or power up recall .................................. 11 switching waveforms .................................................... 11 software controlled store/recall cycle ................ 12 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 package diagrams .......................................................... 14 acronyms ........................................................................ 16 document conventions ................................................. 16 units of measure ....................................................... 16 document history page ................................................. 17 sales, solutions and legal information ....................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc? solutions ...................................................... 18 cypress developer community ................................. 18 technical support ................. .................................... 18 not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 3 of 18 pin configurations figure 1. pin diagram ? 28-pin soic table 1. pin definitions ? 28-pin soic pin name alt i/o type description a 0 ?a 14 input address inputs. used to select one of the 32,768 bytes of the nvsram. dq 0 -dq 7 input or output bidirectional data i/o lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the i/o pins is written to th e specific address location. ce e input chip enable input, active low . when low, selects the chip . when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . a 14 a 12 a 7 a 6 dq 0 dq 1 dq 2 a 3 a 2 a 1 a 13 a 8 a 9 a 11 a 10 dq 7 dq 6 v ss a 0 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ce a 5 a 4 28 27 26 25 v cc we dq 5 dq 3 dq 4 oe (top) not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 4 of 18 device operation the stk15c88 is a versatile memory chip that provides several modes of operation. the stk15c88 can operate as a standard 32 k 8 sram. it has a 32 k 8 nonvolatile element shadow to which the sram information can be copied, or from which the sram can be updated in nonvolatile mode. sram read the stk15c88 performs a read cycle whenever ce and oe are low while we is high. the address specified on pins a 0?14 determines the 32,768 data bytes accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transi- tions on any control input pins, and remains valid until another address change or until ce or oe is brought high. sram write a write cycle is performed whenever ce and we are low. the address inputs must be stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common i/o pins dq 0?7 are written into the memory if it has valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the stk15c88 uses the intrinsic system capacitance to perform an automatic store on powe r down. as long as the system power supply takes at least t store to decay from v switch down to 3.6 v, the stk15c88 will safely and automatically store the sram data in nonvolatile elements on power down. in order to prevent unneeded store operations, automatic stores will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. hardware recall (power up) during power up or after any low power condition (v cc < v reset ), an internal recall request is latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. if the stk15c88 is in a write state at the end of power up recall, the sram data is corrupted. to help avoid this situation, a 10 kohm resistor is connected either between we and system v cc or between ce and system v cc . software store data is transferred from the sr am to the nonvolatile memory by a software address sequence. the stk15c88 software store cycle is initiated by executing sequential ce controlled read cycles from six specific address locations in exact order. during the store cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. when a store cycle is initiated, input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is import ant that no other read or write accesses intervene in the sequence. if they intervene, the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read sequence is performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0fc0, initiate store cycle the software sequence is clocked with ce controlled reads. when the sixth address in the sequence is entered, the store cycle commences and the chip is di sabled. it is important that read cycles and not write cycles are used in the sequence. it is not necessary that oe is low for a valid sequence. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations is performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0c63, initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared, and then the nonvolatile information is transferred into the sram cells. after the t recall cycle time, the sram is once again ready for read and write operations. the recall operation does not alter the data in the nonvolatile elements. the nonvolatile data can be recalled an unlimited number of times. not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 5 of 18 hardware protect the stk15c88 offers hardware protection against inadvertent store operation and sram writes during low voltage conditions. when v cc stk15c88 document number: 001-50593 rev. *e page 6 of 18 table 2. software store/recall mode selection ce we a 13 ? a 0 mode i/o notes l h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output data [1, 2] l h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output data [1, 2] notes 1. the six consecutive addresses must be in the order listed. we must be high during all six consecutive ce controlled cycles to enable a nonvolatile cycle. 2. while there are 15 addresses on the stk15c88, only the lower 14 are used to control software modes. not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 7 of 18 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ?c temperature under bias. ............ ............... ?55 ? c to +125 ?c supply voltage on v cc relative to gnd ... .....?0.5 v to 7.0 v voltage on input relative to v ss ......... ?0.6 v to v cc + 0.5 v voltage on dq 0-7 ................................ ?0.5 v to v cc + 0.5 v power dissipation ........................................................ 1.0 w dc output current (1 output at a time, 1s duration) .... 15 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 4.5 v to 5.5 v industrial ?40 ? c to +85 ? c 4.5 v to 5.5 v dc electrical characteristics over the operating range (v cc = 4.5 v to 5.5 v) parameter description test conditions min max unit i cc1 average v cc current t rc = 25 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0 ma. commercial ? 97 70 ma ma industrial ? 100 70 ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store ?3ma i cc3 average v cc current at t rc = 200 ns, 5 v, 25 c typical we > (v cc ? 0.2 v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. ?10ma i cc4 average current during autostore cycle all inputs do not care, v cc = max average current for duration t store ?2ma i sb1 [3] average v cc current (standby, cycling ttl input levels) t rc = 25 ns, ce > v ih t rc = 45 ns, ce > v ih commercial ? 30 22 ma industrial ? 31 23 ma i sb2 [3] v cc standby current (standby, stable cmos input levels) ce > (v cc ? 0.2 v). all others v in < 0.2 v or > (v cc ? 0.2 v). ? 1.5 ma i ix input leakage current v cc = max, v ss < v in < v cc ?1 +1 ? a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il ?5 +5 ? a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?4 ma 2.4 ? v v ol output low voltage i out = 8 ma ? 0.4 v note 3. ce > v ih will not produce standby current levels until an y nonvolatile cycle in progress has timed out. not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 8 of 18 data retention and endurance parameter description min unit data r data retention 100 years nv c nonvolatile store operations 1,000 k capacitance in the following table, the capacitance parameters are listed. [4] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 0 to 3.0 v 5pf c out output capacitance 7 pf thermal resistance in the following table, the thermal resistance parameters are listed. [4] parameter description test conditions 28-pin soic (300 mil) 28-pin soic (330 mil) unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. tbd tbd ?c/w ? jc thermal resistance (junction to case) tbd tbd ?c/w figure 4. ac test loads 5.0 v output 30 pf r1 480 ? r2 255 ? ac test conditions input pulse levels .................................................. 0 v to 3 v input rise and fall times (10% - 90%)........................ < 5 ns input and output timing referenc e levels ......... .......... 1.5 v note 4. these parameters are guaranteed by design and are not tested. not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 9 of 18 ac switching characteristics sram read cycle parameter description 25 ns 45 ns unit min max min max cypress parameter alt t ace t elqv chip enable access time ? 25 ? 45 ns t rc [5] t avav, t eleh read cycle time 25 ? 45 ? ns t aa [6] t avqv address access time ? 25 ? 45 ns t doe t glqv output enable to data valid ? 10 ? 20 ns t oha [6] t axqx output hold after address change 5 ? 5 ? ns t lzce [7] t elqx chip enable to output active 5 ? 5 ? ns t hzce [7] t ehqz chip disable to output inactive ? 10 ? 15 ns t lzoe [7] t glqx output enable to output active 0 ? 0 ? ns t hzoe [7] t ghqz output disable to output inactive ? 10 ? 15 ns t pu [4] t elicch chip enable to power active 0 ? 0 ? ns t pd [4] t ehiccl chip disable to power standby ? 25 ? 45 ns switching waveforms figure 5. sram read cycle 1: address controlled [5, 7] figure 6. sram read cycle 2: ce and oe controlled [5] t rc t aa t oha address dq (data out) data valid address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc notes 5. we must be high during sram read cycles and low during sram write cycles. 6. i/o state assumes ce and oe < v il and we > v ih ; device is continuously selected. 7. measured 200 mv from steady state output voltage. not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 10 of 18 sram write cycle parameter description 25 ns 45 ns unit min max min max cypress parameter alt t wc t avav write cycle time 25 45 ns t pwe t wlwh, t wleh write pulse width 20 30 ns t sce t elwh, t eleh chip enable to end of write 20 30 ns t sd t dvwh, t dveh data setup to end of write 10 15 ns t hd t whdx, t ehdx data hold after end of write 0 0 ns t aw t avwh, t aveh address setup to end of write 20 30 ns t sa t avwl, t avel address setup to start of write 0 0 ns t ha t whax, t ehax address hold after end of write 0 0 ns t hzwe [7,8] t wlqz write enable to output disable 10 15 ns t lzwe [7] t whqx output active after end of write 5 5 ns switching waveforms figure 7. sram write cycle 1: we controlled [8] figure 8. sram write cycle 2: ce controlled [8] t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 8. if we is low when ce goes low, the outputs remain in the high impedance state. 9. ce or we must be greater than v ih during address transitions. not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 11 of 18 autostore or power up recall parameter alt description stk15c88 unit min max t hrecall [10] t restore power up recall duration 550 ? s t store [6] t hlhz store cycle duration 10 ms v reset low voltage reset level 3.6 v v switch low voltage trigger level 4.0 4.5 v switching waveforms figure 9. autostore/power up recall v cc v switch v reset power-up recall we dq (data out) autostore ? 5v t hrecall t store power-up recall brown out autostore no recall (v cc did not go below v reset ) brown out autostore recall when v cc returns above v switch brown out no store due to no sram writes no recall (v cc did not go below v reset ) note 10. t hrecall starts from the time v cc rises above v switch . not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 12 of 18 software controlled store/recall cycle the software controlled store/recall cycle follows. [11, 12] parameter alt description 25 ns 45 ns unit min max min max t rc t avav store/recall initiation cycle time 25 45 ns t sa [11] t avel address setup time 0 0 ns t cw [11] t eleh clock pulse width 20 30 ns t hace [7, 11] t elax address hold time 20 20 ns t recall recall duration 20 20 ? s switching waveforms figure 10. ce controlled software store/recall cycle [12] t rc t rc t sa t sce t hace t store / t recall data valid data valid 6 # sserdda 1 # sserdda high impedance address ce oe dq (data) notes 11. the software sequence is clocked on the falling edge of ce without involving oe (double clocking will abort the sequence). 12. the six consecutive addresses must be read in the order listed in the mode selection table. we must be high during all six consecutive cycles. not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 13 of 18 ordering information these parts are not recommended for new designs. they are in production to support ongoing production programs only. speed (ns) ordering code package diagram package type operating range 25 stk15c88-nf25itr 51-85026 28-pin soic (300 mil) industrial stk15c88-nf25i 51-85026 28-pin soic (300 mil) stk15c88-sf25itr 51-85058 28-pin soic (330 mil) stk15c88-sf25i 51-85058 28-pin soic (330 mil) 45 STK15C88-NF45tr 51-85026 28-pin soic (300 mil) commercial STK15C88-NF45 51-85026 28-pin soic (300 mil) STK15C88-NF45itr 51-85026 28-pin soic (300 mil) industrial STK15C88-NF45i 51-85026 28-pin soic (300 mil) stk15c88-sf45itr 51-85058 28-pin soic (330 mil) stk15c88-sf45i 51-85058 28-pin soic (330 mil) all parts are pb-free. the above table contains final information . contact your local cypress sales representative for availabi lity of these parts speed: 25 - 25 ns 45 - 45 ns package: s = plastic 28-pin 330 mil soic ordering code definitions stk15c88 - n f 45 i tr temperature range: blank - commercial (0 to 70c) lead finish f = 100% sn (matte tin) i - industrial (-40 to 85c) packaging option: tr = tape and reel blank = tube n = plastic 28-pin 300 mil soic not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 14 of 18 package diagrams figure 11. 28-pin (300 mil) soic, 51-85026 51-85026 *h not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 15 of 18 figure 12. 28-pin (330 mil) soic, 51-85058 package diagrams (continued) 51-85058 *c not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 16 of 18 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance i/o input/output nvsram non-volatile static random access memory oe output enable rohs restriction of hazardous substances sram static random access memory we write enable symbol unit of measure c degree celsius hz hertz khz kilohertz k? kilo-ohm mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt not recommended for new designs. in production to support ongoing production programs only.
stk15c88 document number: 001-50593 rev. *e page 17 of 18 document history page document title: stk15c88 256-kbit (32 k 8) powerstore nvsram document number: 001-50593 revision ecn orig. of change submission date description of change ** 2625096 gvch / pyrs 12/19/08 new data sheet *a 2826441 gvch 12/11/2009 added following text in the ordering information section: ?these parts are not recommended for new designs. in production to support ongoing production programs only.? added watermark in pdf stating ?not recommended for new designs. in production to support ongoing production programs only.? added contents on page 2. *b 3052511 gvch 10/08/10 removed the following inactive parts from the ordering information table: stk15c88-nf25, stk15c88-nf25tr, stk15c88-sf25, stk15c88-sf25tr, stk15c88-sf45, stk15c88-sf45tr updated package diagrams *c 3221180 gvch 04/10/2011 updated package diagrams . updated in new template. *d 3527659 gvch 02/17/2012 package diagrams : updated 28-pin (330 mil) soic package diagram *e 4306736 gvch 03/13/2014 typo fixed ( hardware protect ): changed v cap < v switch to v cc < v switch updated package diagrams : spec 51-85026 ? changed revision from *f to *h. updated in new template. not recommended for new designs. in production to support ongoing production programs only.
document number: 001-50593 rev. *e revised march 13, 2014 page 18 of 18 all products and company names mentioned in this document may be the trademarks of their respective holders. stk15c88 ? cypress semiconductor corporation, 2009-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reaso nably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support not recommended for new designs. in production to support ongoing production programs only.

▲Up To Search▲

Price & Availability of STK15C88-NF45

	To Download STK15C88-NF45 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .